(FORCe)
 

1. Introduction
 

 

The 2001 International Technology Roadmap for Semiconductors (ITRS) indicates that in order to preserve the decades-long trend of 30% per year reduction in cost per function requires taking full advantage of device feature size reductions, yield improvements, wafer size increases, and other manufacturing productivity improvements. Feature size reductions will likely continue at their historic rate over the next several product generations, but reductions from yield improvements and wafer size increases are likely to be lower than their historic rate. Yields are already quite high, so there is not as much room for improvement. The cost of producing larger wafers combined with increased equipment costs negates much of the gains that come from increasing the number of devices per wafer. Therefore, the reductions from other manufacturing productivity improvements must increase to keep overall improvements at historic levels.

In addition to the cost per function requirements described above, the Factory Operations portion of the ITRS indicates that there is increasing pressure on semiconductor manufacturers to reduce cycle times and improve on time delivery (OTD) of products to customers. This section of the ITRS also contains a list of potential solutions to the cost per function and cycle time requirements. The potential solutions are classified into planning decision support tools at the strategic level and tools for running the factory at the tactical or execution level. They identify real-time scheduling as one of the execution level potential solutions. In this paper, we discuss a project aimed at developing a new approach to scheduling wafer fabrication facilities.

2. The Factory Operations Research Center
 

In late 2000, the Semiconductor Research Corporation (SRC) and International SEMATECH announced the development of the Factory Operations Research Center (FORCe). FORCe is aimed at developing enabling technologies to improve factory operations. After reviewing numerous competitive proposals, they decided to fund four projects. Each of the projects is summarized below.

3. Projects

 

A. Demand Forcasting with Multiple Information Sources, and Risk Quantification When Loading Fabrication Facilities
 

 
 
 
 
Robin Roundy
 
 
 
 

B. Preventative Maintenance Scheduling in Wafer Fabs
 

 
 
 
 
Michael Fu, Steven Marcus
 
Emmanuel Fernandez
 
 
 

C. New Approaches for Simulation of Wafer Fabs
 

 
 
 
 
John Fowler, Gerald Mackulak
 
Lee Schruben
 
 
 

D. Demand Data Mining and Planning in Semiconductor Manufacturing Networks
 
 

 
Argon Chen, Shi-Chung Chang, Andy Guo, Yon-Chun Chou
 
 
 

E. Scheduling of Semiconductor Wafer Fabs
 

 
 
 
 
John Fowler, Matt Carlyle, George Runger, Esma Gel, Michele Pfund
 
Scott Mason
 
 
 
Oliver Rose
 
Lars Mönch
 
Roland Sturm
 


Sponsors:
 

 
International SEMATECH
 
Semiconductor Research Corporation
 
 
 
If you have comments or suggestions, e-mail Lauren Fowler at lfowler@ptloma.edu
Site Created: July 2, 2003
Site Last Updated: July 24, 2003